1. Click Netlist above a synthesizable module, or use its Architecture tree entry.
2. Wait for synthesis and layout. The selected module is the netlist top; changing project srcTop is unnecessary.
3. Zoom, fit the diagram and select nodes for the inspector.
4. Read layout warnings; this diagram is not FPGA physical placement.

digital-ide.function.netlist.schema-mode selects before, after or RTL. Start with default before and regenerate after changing modes.

Inspect Output and prj/netlist/<module>.log on failure. Missing packages/includes, nonconstant widths, unsupported syntax, unresolved primitives and nonsynthesizable testbenches are common causes. Language-server support does not imply synthesis frontend support.