Digital IDE provides language services for Verilog, SystemVerilog and VHDL through digital-server. Open the folder that contains your project and check that the language mode in the bottom-right corner of the editor is correct; the features below then work without further setup. Each feature page includes an introduction, a demo video, and the related settings and notes.

Feature	Description
Syntax Highlighting	Distinguish keywords, ports and parameters; gray out code excluded by macros
Symbol Navigation	Browse file structure in the outline and jump to declarations by name
Hover Tooltips	View declarations, ports, constant values and rich comments
Code Completion	Complete symbols, parameters and ports; insert instantiation templates
Go to Definition	Jump from a use to the declaration of a symbol, module, port or parameter
Code Formatting	Normalize Verilog/SystemVerilog and VHDL layout
Live Diagnostics	See errors as you type; turn off diagnostics by code
Inlay Hints	Show port directions and parameter names next to instance connections

If a feature does not work, see Troubleshooting.

Being able to analyze code does not mean it can be synthesized or simulated. Vendor IP, classes, assertions and mixed-language designs are still limited by the actual tools and libraries.