What is code formatting

Code formatting normalizes indentation, line breaks and alignment so parameter lists, port lists and statements follow one consistent layout. Verilog, SystemVerilog and VHDL are all supported.

Right-click in the editor and choose Format Document, or press Shift+Alt+F (Windows/Linux). If several formatters are installed, use Format Document With… and choose Digital IDE.

Demo

Formatting rules

• Verilog/SystemVerilog uses the backend's built-in Verible-compatible style, with the indentation width taken from the editor settings. The old iStyle kr/ansi/gnu styles and command-line arguments have no effect.
• VHDL code in generic, port and architecture is arranged in a consistent style.
• Only whole files can be formatted, not selections.

Notes

Formatting changes layout only; it does not change what connections mean or fix logic errors. If the file has syntax errors, fix the diagnostics before formatting. Review the changes after formatting, then save the file.