Debugger operates on real FPGA ILA/VIO cores. It is separate from processor debugging, offline waveforms and quick simulation. A matching Debug Build, bitstream and probe information are required; a design without debug cores has no channels to capture.

Select the build and core

After adding ILA/VIO attributes to the top-level RTL, click Generate Debug Configuration in the Debugger title bar. Digital IDE parses the active srcTop, creates and opens a matching <srcTop>.debug.toml in the hardware data directory, and never overwrites an existing configuration.

In Debugger, use Refresh Debug Build, then verify vendor, core IDs, probe widths and artifacts. Connect the target and use Read Core Status.

Vivado settings include digital-ide.debugger.vivado.hwServerUrl, .target, .programBeforeAccess and .timeoutMs for server, exact target, programming before access and timeout.

ILA

Choose Capture ILA, wait for trigger/samples and inspect the capture waveform. Use the debug panel's trigger, retrigger and single/continuous controls. Stop ILA Capture stops waiting. Trigger position must be inside the data depth; synthesis-fixed conditions are not editable at runtime.

VIO

Read VIO Inputs reads probes. Write VIO Outputs prompts for each output value as a width-matched bit string or hexadecimal. Check direction, width and hardware function before committing. Stopping ILA does not reset VIO outputs.

Use artifacts from one matching build on manifest/hash/probe errors. The func top in the current temp project contains ILA/VIO test attributes and a default debug configuration for real-board validation.