What are inlay hints

Inlay hints are gray annotations the editor shows next to code; they are not written into the HDL file. In Verilog/SystemVerilog they show:

• the direction (input or output) of each instance port connection;
• the port and parameter names for positional connections;
• the module name after endmodule.

Positional connections omit port names, which makes them hard to read. With inlay hints you can see where each signal connects without jumping to the module definition.

Demo

Enable and configure

First enable Editor: Inlay Hints in VS Code settings, then turn on the Digital IDE hints you need:

{
  "digital-ide.function.lsp.inlayHints.port.connection.enable": true,
  "digital-ide.function.lsp.inlayHints.parameter.assignment.enable": true
}

Setting	Effect
digital-ide.function.lsp.inlayHints.port.connection.enable	Show port directions and port names for positional connections
digital-ide.function.lsp.inlayHints.parameter.assignment.enable	Show parameter names for positional overrides

The current VHDL backend does not provide inlay hints.

When hints are missing

Inlay hints require the instance's target module to resolve. If hints are missing, first use Go to Definition to confirm the instance jumps to its module, then check that parameters resolve.