What is syntax highlighting

Syntax highlighting colors keywords, types, ports, parameters, numbers and comments according to the language rules, so code structure is visible at a glance. Digital IDE supports Verilog, SystemVerilog, VHDL, and constraint files such as XDC.

On top of syntax coloring, Digital IDE adds semantic highlighting from parse results: input and output ports are distinguished by direction, clock and reset ports are marked separately, and code excluded by `ifdef / `ifndef is grayed out so the active branch stands out.

Demo

Language mode

Coloring follows the language mode shown in the bottom-right corner of the editor. After opening a file, check that it matches the file type:

File	Language mode
.v	Verilog
.sv	SystemVerilog
.vhd, .vhdl	VHDL
.xdc and other constraint files	The matching constraint language

Do not change the language mode just to get different colors: the same identifier can be a keyword in one standard and not another. A colored constraint file is not proof that the constraints are applied.

Semantic highlighting settings

Semantic highlighting depends on VS Code's semantic highlighting switch; the actual colors come from the current theme. Port highlighting for Verilog/SystemVerilog can be tuned separately:

Setting	Effect
digital-ide.function.lsp.semantic.tokens.port.clk.rst.enable	Distinguish scalar clock and reset ports
digital-ide.function.lsp.semantic.tokens.port.input.output.enable	Add read/write modifiers based on port direction

Whether a macro branch is grayed out depends on the macro definitions visible during parsing. If a macro is defined in an include file, make sure the include path resolves.

When colors look wrong

Check the language mode, theme, semantic highlighting switch, and whether the file has diagnostics, in that order. A syntax error stops later code from being parsed, and semantic highlighting stops with it.