Prerequisites

Configure toolChain, part, directories and srcTop. Check board constraints, tools and licenses. A processor design needs the real wrapper containing the PS system; setting soc does not insert a processor into a PL-only design.

Xilinx workflow

Entry	Action
Launch	Create/open the project and import HDL, constraints, IP, BD and libraries
Refresh	Synchronize inputs
Build	Synthesis, implementation and bitstream
Synth / Impl / Generate BIT	Individual build stages
Simulate CLI / GUI	Vendor-project simulation
Program / SRAM	Volatile FPGA programming
Flash	Persistent configuration-memory programming
GUI / Exit	Open vendor UI / close the session

Run Launch, then Build, and inspect Output → Digital-IDE Hardware. A persistent Vivado session can still execute source and launch_runs; vendor Tcl scripts are part of that workflow.

Verify outputs

Hover over Build, Synth or Impl and click the chart icon Show build report. The Webview compares resource utilization and displays timing slack, on-chip power and DRC violations from the current Vivado project's report files. It refreshes while open, includes a manual refresh button and lets you open the original reports.

Resource reports show their stage and timestamp. Reports from before the current run or with a different top/part are excluded from charts. Missing metrics remain unavailable; timing inf is shown as having no finite value. A completed Synth/Impl run does not imply that a bitstream was generated. This view currently supports Vivado reports.

Check the actual bitstream, top level, DRC and timing reports. The Xilinx flow exports a hardware handoff for SDK; PS designs need processor metadata and initialization files. The default handoff location is user/sdk/data; use the actual Output path.

The current HDF/write_hwdef flow produces a deprecation warning in Vivado 2022.2. Check that a current readable file exists, rather than treating either a printed path or a deprecation warning as the final result.

Programming and other toolchains

Verify power, board and JTAG target before Program. Flash requires matching configuration-memory parameters in property.json.flash; volatile programming does not prove persistent boot.

For Efinity use toolChain: "efinity", a supported part and a valid Efinity installation. Its pin/device database and workflows differ from Xilinx; XDC, BD and PS/SDK instructions cannot be transferred unchanged.

UCIO-1 requires correct pin constraints. Locked IP requires checking tool revision and part compatibility. On failures read the first relevant error and avoid stale artifacts.

Configure Xilinx IP in a Webview

With property.json.toolChain set to xilinx, open HARD Options → Configure Xilinx IP (also available in the command palette). Set device and digital-ide.prj.vivado.install.path first. IP queries accept an installation directory, bin directory or executable. Prefer bin or a full executable path for compatibility with HARD Launch. Explicitly set an empty string to use PATH instead of the historical default; see Toolchain path configuration.

Search the installed Vivado catalog by name or VLNV, choose an IP, and edit its parameters. Custom IP_REPO repositories are included. Validate and update parameters runs Vivado's parameter checks and reads back propagated values. ILA/VIO probe fields beyond the configured probe count are hidden by default; validate after changing the count.

Run HARD Launch and wait for Ready, then choose a module name and output parent directory and generate. Outputs are written to <parent>/<module>/<module>.xci with the IP's supported synthesis, simulation and instantiation targets. The default parent is the ip sibling of arch.hardware.src (user/ip in the default project). Existing module directories are never overwritten. This does not synthesize the complete project or modify property.json. Generation runs in the already-launched Vivado process and adds the IP to the current project immediately. References survive Refresh within that HARD session. External output paths still require project input configuration for automatic discovery after restarting the extension.

The theme-aware form uses actual CONFIG.* values and IP metadata. It does not embed Vivado's native window or reproduce vendor-specific diagrams and wizard widgets. Vivado remains the authority for parameter validation and licensing. Click an IP in Architecture to edit its existing XCI in the configuration page. The module name and output location stay fixed. Preview operates on a temporary copy; Save and Regenerate updates the original IP in the Ready HARD session. External XCI edits are detected before saving. Failed or cancelled saves restore the original XCI and stop the HARD session; Launch again and regenerate outputs before building. Locked IP version upgrades still require Vivado. Catalog/parameter previews reuse an isolated Vivado worker. Generation requires an idle, matching HARD project; it never silently launches another process. Cancelling generation or closing the generating panel stops the shared HARD session and removes incomplete output, so Launch is required again. Cancelling a preview affects only the preview process. Logs appear in Digital-IDE Hardware.

Native XGUI reconstruction

The HTML renderer now captures pages, groups, tables, widget properties and callback results by executing installed XGUI scripts inside Vivado. Encrypted Tcl remains within Vivado; vendor scripts are not decrypted or shipped with the extension. No remote desktop streaming is involved.

ILA/VIO probe pages, table visibility and width diagrams, and Binary Counter pages are supported. FFT pages are extracted, but its native resource estimator still requires a VIP context. Clocking Wizard's legacy callbacks have remaining compatibility gaps. The PS7 adapter supplies functional sections and a 54-pin MIO electrical-settings matrix; it does not yet reproduce peripheral routing, DDR wizards or the original clock diagram. Graphs use actual exported numeric series; image loading is restricted to the corresponding IP directory. Unsupported operations are listed in the panel instead of silently claiming full parity.

This is not a complete recreation of every Vivado GUI. Validate after edits to update callback-dependent layout and diagrams. The preview worker stays alive between requests, while each request uses a fresh temporary project to isolate IPs and failed edits. Catalog results are cached for five minutes by executable, part and custom repositories; Refresh Catalog bypasses this cache, including after custom repository edits. Closing the panel, cancelling a preview or leaving it idle for two minutes releases the worker. Cold startup and first-time loading of complex IP scripts still take time; Hardware output reports request durations.

The IP Webview follows the active VS Code light, dark or high-contrast theme, including form controls, tables, tabs and SVG charts. Switching themes updates the open panel without resetting edits. Vendor raster images retain their original contents.