Prerequisites

Complete HARD first. Verify that the actual top contains a processor and that the hardware handoff matches the bitstream. Set digital-ide.prj.xsdk.install.path to compatible XSCT/Vitis tools.

For bare-metal Zynq-7000, update the relevant soc fields:

{
  "soc": {
    "core": "ps7_cortexa9_0",
    "os": "standalone",
    "app": "Hello World"
  }
}

app also accepts a template array; use Select ELF for multiple applications. Supported systems/templates depend on the processor and tool installation.

Build and download

1. SOFT Options → Launch reads the handoff and creates/updates the platform and applications.
2. Build compiles BSP/application outputs.
3. Select ELF chooses the current application and processor.
4. Download offers matching bitstream programming, initializes the processor and downloads ELF.
5. Check Output and target state. Hello World UART verification requires a separate connection; Running alone is insufficient.

Control and GDB

SOFT Options uses property.json soc.core to show only the matching processor controls. For example, ps7_cortexa9_0 selects Zynq-7000, while ZynqMP A53/R5 and MicroBlaze use their own entry.

Status reads state; Halt/Stop pauses, Run resumes and Reset resets without rebuilding.

Configure the service with digital-ide.xilinx.ps.hwServer.* and the matching debugger/ports with digital-ide.xilinx.ps.gdb.*. After Generate Configuration or Start and Prepare creates the debug configuration, select the Digital IDE: ... configuration and press F5 directly. F5 starts or reuses hw_server, resets and initializes the target, optionally programs the bitstream, and then asks GDB to load the ELF. The generated cppdbg configuration requires the Microsoft C/C++ extension ms-vscode.cpptools, which is included in the Digital IDE extension pack.

After rebuilding C/C++ sources at the same ELF path, F5 can be used again directly. Regenerate the configuration after changing the hardware handoff, processor, ELF path, or bitstream mode, and verify that the configuration still points to the current ELF and processor.

For download failures check JTAG, target selection, PS initialization, ELF architecture and hardware handoff in that order.

F5, downloads and processor controls perform a read-only hardware preflight, checking JTAG/processor enumeration as well as TCP endpoints. Empty targets or connection failures trigger one reconnect. If that fails and the current Digital IDE session owns the server, it restarts that server once and checks again. External servers are not terminated; Output → Digital-IDE Software reports the endpoint and recovery guidance. MicroBlaze downloads check JTAG first because the soft processor may only appear after programming the bitstream. Missing or ambiguous processor matches stop the operation.