What is code completion

Code completion offers candidates to insert at the cursor, filtered by context: in an expression it offers signals and parameters visible in the current scope, inside an instance's parameter list only the target module's parameters, and in port connections only the target module's ports. Type the name of a project module or vendor primitive and you can insert a full instantiation template, including the parameter list and every port connection.

Candidates appear as you type; press Ctrl+Space to open the list manually, then accept with Tab or Enter.

Demo

Completion types

Type	Where to trigger	Candidates
Symbol	Type a name in an expression	Signals, parameters and other symbols visible in the current scope
Instantiation	Type a module or vendor primitive name	Instantiation template with parameter list and port connections
Parameter	Type . inside an instance #(...)	Target module parameters
Port	Type . inside instance port connections	Target module ports with their directions
System task	Type $	System tasks and functions
Preprocessor	Type a backtick `	Preprocessor directives and visible macros
Path	Inside an include string	Available files and directories

An instantiation template is only a starting point: after inserting it, review each parameter, port, width and connected signal. Primitive candidates come from the vendor primitive library provided by the backend; seeing a candidate such as IBUF does not mean the design can use it on every device.

Other ways to instantiate

Besides typing the module name, you can use TOOL Options → Instantiate Module or the command Generate instance template from selected module (Alt+I), then pick the target module to insert an instance at the cursor.

Custom snippets

The extension ships HDL snippets; for snippets with placeholders, press Tab to move to the next one. Create your own with VS Code Configure User Snippets, in a language snippet file or a workspace .code-snippets file:

{
  "Clocked register": {
    "prefix": "dide_reg",
    "body": ["always_ff @(posedge ${1:clk}) begin", "    ${2:q} <= ${3:d};", "end"],
    "description": "Clocked register"
  }
}

Save it as a SystemVerilog user snippet, then type dide_reg in an .sv file. Snippets are not stored in property.json.