Prepare a testbench

Choose a testbench with stimulus and a termination condition. For an offline VCD use $dumpfile, $dumpvars and $finish:

initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, tb);
    #1000;
    $finish;
end

Start and advance

Use the testbench Simulate CodeLens or Architecture simulation entry. The backend resolves dependencies, compiles and connects an interactive simulator. Click run/start to advance time; compilation alone does not execute the testbench. Set a step amount, pause or restart as needed.

The simulation sidebar supports stimulus and clocks for driveable inputs. Check signal widths before applying values. Open the generated VCD for offline viewing or add live subscribed signals.

UART stimulus and decoding

The interactive simulation sidebar contains stimulus, clocks and UART encoders/decoders. Select a driveable input for transmission, or an observed signal for decoding, then configure matching baud rate, data bits, parity and stop bits. Advance simulation before inspecting results. Match clock/stimulus timing to the simulation units; editing stimulus does not regenerate an existing offline VCD.

Backend selection

digital-ide.function.simulate.fastSimulator selects verilator, iverilog, cxxrtl, vcs, modelsim or questa; install the corresponding tools. The VHDL entry selects ModelSim. See Toolchain path configuration.

Mixed HDL and vendor IP need compatible simulation libraries. digital-ide.function.simulate.xilinxLibPath specifies Xilinx libraries; vendorCachePath is deprecated; current vendor simulation caches live under the project’s .dide/ directory. HARD Simulate CLI/GUI operates on the vendor project instead.

For missing modules check dependencies; for missing VCD check dump calls, working directory and actual execution. Add signals before judging an empty view; subscriptions do not recreate uncollected history.