Digital IDE uses a bundled Yosys frontend to render synthesizable RTL modules as interactive logic netlist diagrams without requiring external synthesis tools.

1. Demonstration

In ch05, the netlist top is demo_top, using the accuml instance added in ch03. The video generates the full hierarchy from CodeLens, collapses u_accuml in hierarchy navigation, fits the view, and demonstrates hover focus, node/wire selection and RTL navigation (generated by bundled Yosys without requiring Vivado).

2. Generating a netlist

1. Open the target HDL file and click the Netlist CodeLens above a synthesizable module, or right-click the module in Architecture and select Netlist (the selected module becomes the netlist top without changing project srcTop).
2. Optional: configure digital-ide.function.netlist.schema-mode to before (default), after, or RTL, then regenerate.

3. Netlist view interactions

The initial diagram includes the complete hierarchy, with u_accuml expanded. Click an instance in hierarchy navigation to expand/collapse its internals; use zoom and fit controls to frame the diagram.

Interaction	Action	Behavior
Hover focus	mouseover a node, port, or wire	Highlights the connected fanout, junction, ports, nodes, and ancestor nodes while dimming unrelated paths.
Hover tooltip	Hover over a node or port	Shows its name, direction/width information and source location (for example, hovering clock shows input · 1 bit · demo_top.v:3).
Single / multi-select nodes	click to select; Ctrl+click to toggle multi-selection	The inspector shows name, path, type, layout coordinates, size, layer/order, src and parameters. With multiple selections, it displays the last selected instance.
Select wire / fanout	Click a wire or nearby blank space within a few pixels	Snaps to and selects the fanout; the inspector shows its driver and Route Arc count (for example, clock · clock and ~ 1b · Y each show 1 arc).
Jump to RTL source	Click a node (without Ctrl) or press Enter after selecting it	Opens the corresponding HDL file in the editor and selects the matching RTL range.

Selecting the not node and pressing Enter jumps to ~reset_n on line 7 of demo_top.v; clicking u_accuml selects its instantiation on lines 17–24.

4. Troubleshooting

Inspect Output → Digital-IDE and prj/netlist/<module>.log on failure. Missing packages/includes, non-constant widths, unsupported behavioral syntax, unresolved vendor primitives, and non-synthesizable testbenches are common causes.