This guide takes a source directory to usable hardware artifacts. Xilinx uses Vivado; Efinix uses Efinity. Their parts, constraints and project formats differ. After building, use HARD programming to write the board.

Jump to device selection, HDL libraries, filelist import/export, Xilinx projects, or Efinix projects.

Common creation steps

1. Open the project root with File → Open Folder.
2. Choose TOOL Options → Create Project Configuration, enter a name and select xilinx or efinity. Edit an existing .vscode/property.json directly.
3. The command creates .vscode/property.json, prj/ and the standard user/ directories. Put design HDL in user/src, testbenches in user/sim, and board data/constraints in user/data. Use arch to retain another layout.
4. Replace the initial device: "none" with the actual part and choose design/simulation tops in Architecture. A top is a module/entity name, not a filename.
5. Configure tool paths, then check dependencies, pins and clocks.

Watch project creation in Activation and minimal configuration. Chapters ch01–ch06 build on the same demo_project (with device: "xc7z010clg400-1", srcTop: "demo_board", and simTop: "demo_tb"). See the configuration reference for full field descriptions.

Device selection

Set toolChain in .vscode/property.json, place the caret inside the device string and type a prefix or press Ctrl+Space.

Select family → chip → package → full part/speed grade. Intermediate selections reopen suggestions; longer prefixes skip directly to a matching stage. Suggestions use unsaved toolChain edits as well.

Toolchain	Bundled catalog
xilinx	4,131 real Vivado 2022.2 parts across 41 returned families/variants
efinity	360 parts from Efinity June 2024, covering Trion and Titanium; completion also accepts efinix

No local vendor installation is needed for suggestions. device remains free-form: requesting suggestions does not validate parts, save the document or rewrite other fields. Type newer parts manually when needed; actual support depends on the installed tool. Use efinity for hardware builds.

HDL library reuse

Bundled HDL libraries let projects reuse module sources. Import the required members, then instantiate the modules in your HDL. Importing adds dependencies; it does not create instances or connect ports.

Common and custom libraries

Click the library import button at the upper right of the Architecture header (tooltip: Import HDL Libraries (References)), or run the same command from the Command Palette, to open the library browser:

Entry	Contents	Root
common	Extension-provided HDL sources	Bundled location, optionally overridden by digital-ide.lib.common.path.
custom	Your own shared HDL sources	digital-ide.lib.custom.path, or a directory selected temporarily.

These are HDL source libraries, separate from Vivado's IP Catalog and a simulator's precompiled vendor libraries. See toolchain settings for library root settings.

Browse and import

1. Select common or custom and press Enter.
2. Enter subdirectories with Enter; choose ... to go back. Directory rows show README summaries.
3. Click the import button on the right of the desired file or directory. A directory imports all its HDL descendants; a root can import the whole library. Prefer specific modules to avoid unnecessary sources.
4. Imported entries show their imported state, and the browser stays open. Press Esc, then inspect the Architecture hierarchy.

Browsing alone does not change the project. Once you click import, references are saved; closing the browser does not undo them.

Use an imported module

Read its README, parameters and ports, then instantiate it in your HDL using editor instantiation tools or a handwritten instance. Check dependencies and verify the interface through simulation or synthesis.

Importing Basic/Math/FixedPoint/accuml.v saves a reference like this:

{
  "library": {
    "state": "remote",
    "hardware": {
      "common": ["Basic/Math/FixedPoint/accuml.v"],
      "custom": []
    }
  }
}

Merge this fragment into the existing property.json. Check the actual source for companion dependencies: importing one file does not import every file in its directory.

Custom roots and paths

When digital-ide.lib.custom.path is set, relative custom references resolve against that root. Otherwise select custom or the folder button to choose an existing directory temporarily; those imports use absolute paths.

Common references resolve against the common library root. Absolute custom paths are used directly. Every team member needs a resolvable library root; personal absolute paths may not exist on another machine.

Remove references and edit sources

Imported rows have a remove button. Removing a reference does not delete library sources. Removing a directory-covered member keeps its siblings. You can also edit library.hardware.common or custom manually.

Sidebar imports preserve existing configuration and comments, append the corresponding references, and set library.state to remote. This mode references external library locations; it does not require a network connection or download/copy sources into the project. Editing shared sources affects every referencing project.

Troubleshooting

Symptom	Check
Empty common/custom directory	Resources and configured roots; Remote SSH needs remote paths.
No instance after importing	Instantiate the imported module in the design.
Missing module or package	Companion files, include paths and macro definitions.
Duplicate module	Sources discovered both as a local copy and external library, or multiple imported versions.

See Configure and edit Xilinx IP below for vendor IP, and the field reference for library fields.

HDL library import and instantiation demo

The video locates the library import button in the Architecture header, browses common → Basic → Math → FixedPoint and imports accuml.v with its row button. It then checks the new accuml node under src and the saved library reference, inserts an instance with TOOL Options → Instantiate Module, sets WIDTH = 16, and shows the connected ports.

Filelist management

Export dependencies

Right-click a module in Architecture, choose export filelist, and save a .f file. The tree entry roots dependencies at that module; a direct command uses the workspace scope. Review paths, defines and include directories for compatibility with the receiving tool.

Import

Run import filelist and select a .f, .fl or .filelist file. The command merges the parsed sources, include directories and macro definitions into files and filelist in property.json, reporting any unsupported entries in Output while preserving unrelated settings.

Paths inside an imported list resolve relative to that list's directory. Check external libraries when moving lists between machines.

The demonstration opens sources.f, presses F1 to run Digital-IDE: import filelist, selects the list and checks the merged configuration. It adds rtl/sample_counter.v to files.src, include to filelist.includeDirs, DEMO_MODE: "1" to filelist.defines, and sources.f to filelist.sources; sample_counter then appears in Architecture.

Xilinx: create and configure

Prepare inputs

A PL-only example:

{
  "toolChain": "xilinx",
  "prjName": { "PL": "demo" },
  "device": "xc7a35tftg256-1",
  "srcTop": "top",
  "simTop": "top_tb",
  "soc": { "core": "none" }
}

Omit arch for the standard layout. For a custom layout, specify all design, simulation, data and software directories so editor discovery and vendor inputs stay aligned.

Input	Location / configuration
Design HDL	user/src, or additional files through arch / files.src.
Pins and timing	XDC in user/data, matching the board's pins, electrical levels and clocks.
HDL libraries	Import common/custom members using HDL library reuse.
Vendor IP / BD	Defaults: user/ip, user/bd. Use IP_REPO for custom packaged IP repositories.
Vivado	digital-ide.prj.vivado.install.path, preferably a bin directory or full executable path.

Back up existing Vivado projects before converting them with the extension's conversion command; see the interface guide.

Launch, synchronize and build

Order	HARD Options entry	Check
1	Launch	Creates/opens the vendor project and imports HDL, constraints, IP, BD and libraries. Wait for Ready.
2	Refresh, when inputs change	Synchronizes configuration and inputs with Vivado.
3	Build	Runs synthesis, implementation and bitstream generation. Inspect each stage.
As needed	Build → Synth / Impl / BitStream	Runs individual stages to isolate failures; preceding artifacts must be valid.
As needed	Simulate → CLI / GUI	Vendor-project simulation, separate from fast interactive simulation.
Finish	Exit	Ends the project session.

Inspect the working directory, executed commands and logs in Output → Digital-IDE Hardware. After adding source files, libraries or constraints, click Refresh before running Build.

Xilinx full flow: toolchain validation to SRAM programming

Recorded with Digital-IDE 0.5 and Vivado 2022.2 on the same demo_project built up in the previous chapters: minimal Xilinx project structure, Launch, Refresh, synthesis, implementation, bitstream generation, the visual build report and FPGA SRAM programming (for tool-path setup and validation see Toolchain path configuration; for Flash configuration see HARD programming). Build waits are shortened. The demo_board top uses only the configuration clock STARTUPE2/CFGMCLK and drives no package pins.

Stage	Completion evidence	What to analyze
Refresh	Ready; sources, constraints and IP synchronized to the Vivado project.	Confirm that all added sources, constraints and IP are imported.
Synth	synth_design completed successfully and a synthesized checkpoint.	Inspect errors, critical warnings and ordinary warnings.
Impl	route_design completed successfully; All user specified timing constraints are met.	Check the routed report and timing constraint coverage. This run achieves WNS 8.378 ns, WHS 0.155 ns, TNS/THS 0 and zero failing endpoints.
BitStream	write_bitstream completed successfully and a new demo_project.bit in the project root.	Routed DRC reports 2 warnings, 0 errors: ZPS7-1 (PL-only example without PS7) and RTSTAT-10 (counter output has no pin loads). Review the DRC report items after generation.
Program → SRAM	hardware/program: completed; JTAG status readback gives DONE=1, INIT_B=1, CRC_ERROR=0.	Confirm FPGA configuration completion and verify board behavior (use Flash programming for nonvolatile boot).

The example uses xc7z010clg400-1. Because JTAG identification reports only the device family, always set device to the full part number (including package and speed grade) from your board schematic, and supply the corresponding clock, pin and electrical constraints in your XDC file.

Configure and edit Xilinx IP

For toolChain: "xilinx", click HARD Options → IP Catalog to open the Xilinx IP configuration page (also available in the Command Palette as Digital IDE: Configure Xilinx IP).

1. Set device and the Vivado path. Run HARD Launch and wait for Ready; subsequent IP configuration and generation steps reuse this session.
2. Open IP Catalog and search the installed catalog by name or VLNV; custom IP_REPO entries are included.
3. Select an IP, enter its module name and parameters, then click Verify and update parameters. Vivado validates values and updates dependent parameters. Verify again after changing ILA/VIO probe counts.
4. Choose an output parent and click Generate IP. The default is the ip sibling of the source directory (user/ip in the standard layout). After generation, inspect <parent>/<module>/<module>.xci and the generated .veo / .vho instantiation template.
5. Connect its instance in HDL and build. Generated IP is added to the current Vivado session. Add external output directories to discoverable inputs so they can be reimported after a restart.

Click an existing IP/XCI in Architecture to edit it. Module name and output location remain fixed. Validate before Save and Regenerate. Preview uses a temporary copy; saving detects external XCI edits. Locked IP upgrades still require Vivado.

Generation requires an idle, Ready session matching the project and part. Existing directories are not overwritten. Cancelling generation, closing its active page or failing to save an existing IP stops HARD and cleans/restores the relevant files; Launch again. Cancelling parameter preview only stops preview work.

IP configuration page support

The HTML form reconstructs pages, groups, tables, choices and some dynamic charts. It follows the VS Code theme and asks the installed Vivado to validate parameters, without streaming the vendor desktop.

ILA/VIO probe tables and width diagrams, as well as Binary Counter pages, are supported. For complex wizard-based IPs (such as Clocking Wizard or PS7), the panel lists the supported parameter controls.

Catalog queries and previews reuse an isolated Vivado worker; generation uses the launched HARD session. Catalog caching lasts five minutes and can be refreshed after repository changes. Closing or two idle minutes releases the preview worker. Cold IP loading can take time; inspect Hardware output. Vivado still enforces licensing.

Xilinx IP configuration and generation demo

The video starts by expanding HARD Options and running Launch; once the session is Ready it opens IP Catalog, searches for xlconstant, names it step_constant, sets CONST_WIDTH = 16 and keeps CONST_VAL = 1.

After parameter verification it generates user/ip/step_constant/step_constant.xci and inspects the .veo template. In demo_top.v it then types step_c, selects step_constant · module instantiation and presses Enter to insert the instance, connecting dout to the same-named 16-bit signal. Finally it checks step_constant under u_top in Architecture. Vivado start-up and catalog loading waits are shortened.

If generated IP wrappers trigger timescale or vendor-dependency diagnostics in the editor, inspect the Vivado generation and synthesis logs.

Inspect reports and artifacts

Hover over Build / Synth / Impl and click Show build report to inspect Vivado resource utilization, timing slack, power and DRC summaries, or open the raw report files.

The current flow writes the programming bitstream to <prjName.PL>.bit in the workspace root. Check Output, the actual artifact and its timestamp before programming.

Processor designs also export a hardware handoff file (under user/sdk/data by default) during bitstream generation; continue with SDK and processor debugging.

Efinix project creation and builds

Efinix is the vendor; Efinity is its software. Use toolChain: "efinity":

{
  "toolChain": "efinity",
  "prjName": { "PL": "demo" },
  "device": "Ti180J484C4",
  "srcTop": "top",
  "simTop": "top_tb",
  "soc": { "core": "none" }
}

Use device selection to choose the part number, package and speed grade matching your target board, and configure the corresponding pin bindings and SDC timing constraints.

Select the execution mode

Mode	Setting	Current behavior
Original Efinity	digital-ide.efinity.install.path: original installation root	Launch/Refresh generates XML, ISF and SDC and runs Interface Designer. Continue synthesis and implementation in original Efinity.
Self-contained package	Original path empty; digital-ide.prj.efinix.package.path: valid package root	Backend synthesis, placement/routing and artifact generation using packaged tools and device resources.

A non-empty original installation path takes precedence even when a package is configured. Clear it in the effective settings scope to use package mode. Original mode does not currently execute HARD Build, SRAM or FLASH and does not silently fall back to the package.

Original mode: generate the vendor project

1. Install Efinity, configure its root, and check bin/efinity and bin/efx_run.
2. Set project name, device, design top and source directories, with at least one design HDL file.
3. Prepare rust/efinity.defaults.toml and rust/pins.toml under the data directory. They hold interface/electrical defaults and board resource/pin bindings. Port names must match the HDL top. Use SDC for timing constraints.
4. Run HARD → Launch. It generates prj/efinity/<name>.xml, .isf, .sdc, .sources.json, then invokes original Interface Designer to produce .peri.xml.
5. Check generated paths and Interface Designer results in Output. Open the generated XML project in original Efinity for synthesis, implementation and artifact generation. Use supported vendor programming tools for this mode.
6. After source, interface or pin changes, Refresh, inspect generated output, and continue the vendor build.

If missing TOML files or invalid pin bindings cause Launch to fail, fix the configuration reported in Output and run Refresh.

Package mode: build in the extension

1. Prepare a complete valid package on a supported host. Current packaged backend resources are Linux tools; bin, lib, arch and res must match. Copying only executables is insufficient.
2. Clear the original installation path, set the package root and verify device resources/version checks.
3. Configure property.json, RTL and SDC. For interface generation, prepare user/data/rust/design.toml or use efinity.interfaceConfig to select its actual path. Existing interface artifacts must also match the current design and device.
4. Launch validates the project/package; Refresh updates changed inputs. Run Build, or Synth → Impl → BitStream individually.
5. Check <name>.bit / .hex and reports under default prj/efinity/outflow, using the actual task result and current files.

The build stages run efx_map (synthesis), efx_pnr (placement and routing) and efx_pgm (image file generation). Use fast simulation to run testbenches.

Back up and isolate old artifacts when changing modes to avoid reusing another mode's outputs. Package programming has additional device-family and connection requirements; see HARD programming.

Troubleshoot a build

Symptom	Check
Missing module, package or include	Source directories, top, library references, include paths and macros.
UCIO-1 / unconstrained IO	Board pin/electrical constraints; fix them instead of lowering DRC severity.
Locked Xilinx IP	Vivado/IP revision and target part; upgrade in Vivado if needed.
Unsupported Efinity action	Whether original mode is selected and Build/Program is implemented for that mode.
Artifact path printed but task failed	Inspect the earliest ERROR line in Output → Digital-IDE Hardware and verify the artifact's modification timestamp.

Interface guide · Configuration reference · HDL libraries · HARD programming