Expansion Modules
About 1190 wordsAbout 4 min
2026-11-14
Expansion modules connect to the core board through top-layer J1 and J2. This page gives the mandatory power rules, available signals and trace lengths for expansion module design, plus the RF-AD9361 RF module pin mapping. For pin assignments, see Pinout; for connector coordinates, see Mechanical.
Mating Connectors
| Item | Requirement |
|---|---|
| Core board side | J1, J2: Hirose DF40C-60DP-0.4V(51) headers, top layer |
| Module side | 2 × Hirose DF40 series 60DS-0.4V(51) receptacles; board-to-board spacing depends on the receptacle model, for example 3.0 mm with DF40HC(3.0)-60DS-0.4V(51) |
| Position | Connector centers 14.03 mm apart, aligned in X; module-side coordinates are a left-right mirror of the core board top-layer coordinates |
| Pin 1 | Receptacle pin 1 faces header pin 1; J1 / J2 pin 1 is at the left end in the core board top view |
VCCIO Supplied by the Expansion Module
The FPGA Bank 1B and Bank 3A I/O supplies are not generated on the core board. They are routed to J2, and the expansion module sets their voltages:
| Pins | Net | Function |
|---|---|---|
| J2.40 / J2.42 | VCCIO1B | Bank 1B (L09 – L13, L17, L18 on J2) and TEST_N, NSTATUS pull-ups |
| J2.39 / J2.41 | VCCIO3A | Bank 3A (R10 – R14 on J1) and MCU UART7 |
| J2.36 / J2.38 | VDD_1V8 | Core board 1.8 V output; can connect directly to the two groups above |
- For 1.8 V I/O, connect J2.36 / 38, J2.39 / 41 and J2.40 / 42 together on the module. RF-AD9361 uses this arrangement.
- For other I/O voltages, generate them on the module and connect them to VCCIO1B / VCCIO3A. Voltages must be within each bank's permitted VCCIO range (see the Efinix Ti60 datasheet); do not also connect them to VDD_1V8.
- Without an expansion module, TEST_N loses its pull-up, and Bank 1B / 3A have no I/O supply. To debug the core board alone, use an adapter board or jumper wires to connect J2.39 – J2.42 to J2.36 / J2.38.
Available Power Rails
| Rail | J2 pins | Source |
|---|---|---|
| 5V | 52 / 54 / 56 / 58 / 60 | Directly connected to J3 5V; the module can draw power here or supply the core board (for example, through RF-AD9361 USB-C) |
| VDD_3V3 | 44 / 46 / 48 / 50 | TMI7003 CH2 |
| VDD_1V8 | 36 / 38 | TMI7003 CH1 |
| VDD_1V2 | 28 / 30 | TMI7003 CH3 |
Bidirectional 5V
J2 and J3 5V are directly connected on the core board, without reverse-current protection. The module and base board must not both supply 5V unless one side has an ideal diode or power-selection circuit.
Signals and Trace Lengths
J1 provides 12 differential I/O pairs and J2 provides 9, all routed at 100 Ω differential impedance. The table below gives core board trace lengths from FPGA balls to connector pads (from the PCB, excluding vias and in-package lengths). Include these lengths when matching traces within a signal group on the module. For in-package lengths, use the Efinix Ti60 net length table (F100S3F2 has two versions depending on lot number).
| Differential pair | Connector | P / N length (mm) |
|---|---|---|
| R02 | J1 | 9.58 / 9.26 |
| R03 | J1 | 9.04 / 9.01 |
| R04 | J1 | 10.86 / 10.81 |
| R06 | J1 | 10.42 / 10.81 |
| R07 | J1 | 10.06 / 9.88 |
| R08 | J1 | 9.47 / 9.47 |
| R09 | J1 | 10.12 / 10.34 |
| R10 | J1 | 8.48 / 8.25 |
| R11 | J1 | 10.20 / 10.63 |
| R12 | J1 | 10.95 / 10.31 |
| R13 | J1 | 8.82 / 8.64 |
| R14 | J1 | 10.32 / 10.69 |
| L05 | J2 | 11.34 / 11.60 |
| L06 | J2 | 12.12 / 12.72 |
| L09 | J2 | 11.42 / 11.45 |
| L10 | J2 | 12.60 / 12.83 |
| L11 | J2 | 11.82 / 11.69 |
| L12 | J2 | 11.57 / 12.18 |
| L13 | J2 | 12.47 / 12.65 |
| L17 | J2 | 11.18 / 11.26 |
| L18 | J2 | 12.01 / 12.23 |
J1.3 (SYNC_IN), J1.4 / J1.6 (USB) and J2.24 (CRESETN) also connect to the module. USB connects in parallel with the MCU; the module can pull CRESETN low to reset the FPGA. J1.5, J1.33 / 35 / 39 / 41 / 45 – 48 / 52 / 54 / 56 / 58 and J2.16 / 18 / 22 / 33 – 35 / 55 / 57 are not connected on the core board.
RF-AD9361 Pin Mapping
RF-AD9361 plugs directly into J1 / J2. The module connects VDD_GPO (J2.36 – J2.42) together, so core board VDD_1V8 powers both AD9361 VDD_INTERFACE and FPGA Bank 1B / 3A. The digital interface level is 1.8 V.
LVDS Data Interface
| AD9361 signal | Connector pins (P / N) | Core board net | FPGA balls (P / N) | FPGA pin names (P / N) | Bank |
|---|---|---|---|---|---|
| DATA_CLK | J2.3 / J2.5 | L09_P / L09_N | F3 / F2 | GPIOL_P_09_CLK2_P / GPIOL_N_09_CLK2_N | 1B |
| RX_FRAME | J2.4 / J2.6 | L05_P / L05_N | G4 / G3 | GPIOL_P_05 / GPIOL_N_05 | 1A |
| RX_D0 | J2.15 / J2.17 | L11_P / L11_N | E2 / E3 | GPIOL_P_11 / GPIOL_N_11 | 1B |
| RX_D1 | J2.45 / J2.47 | L18_P / L18_N | B3 / B2 | GPIOL_P_18_PLLIN0 / GPIOL_N_18 | 1B |
| RX_D2 | J2.27 / J2.29 | L13_P / L13_N | B1 / C1 | GPIOL_P_13_CBSEL0 / GPIOL_N_13_CBSEL1 | 1B |
| RX_D3 | J2.9 / J2.11 | L10_P / L10_N | E1 / D1 | GPIOL_P_10_CLK3_P / GPIOL_N_10_CLK3_N | 1B |
| RX_D4 | J2.10 / J2.12 | L06_P / L06_N | G1 / F1 | GPIOL_P_06 / GPIOL_N_06 | 1A |
| RX_D5 | J2.21 / J2.23 | L12_P / L12_N | C3 / C2 | GPIOL_P_12 / GPIOL_N_12 | 1B |
| FB_CLK | J1.27 / J1.29 | R11_P / R11_N | D8 / D9 | GPIOR_P_11_CLK8_P / GPIOR_N_11_CLK8_N | 3A |
| TX_FRAME | J1.10 / J1.12 | R04_P / R04_N | H10 / G10 | GPIOR_P_04_CDI28 / GPIOR_N_04_CDI29 | 3B |
| TX_D0 | J1.34 / J1.36 | R12_P / R12_N | D10 / C10 | GPIOR_P_12 / GPIOR_N_12 | 3A |
| TX_D1 | J1.22 / J1.24 | R09_P / R09_N | E8 / E9 | GPIOR_P_09_CLK10_P / GPIOR_N_09_CLK10_N | 3B |
| TX_D2 | J1.16 / J1.18 | R07_P / R07_N | G8 / F8 | GPIOR_P_07 / GPIOR_N_07 | 3B |
| TX_D3 | J1.15 / J1.17 | R02_P / R02_N | J8 / J7 | GPIOR_P_02_CDI24 / GPIOR_N_02_CDI25 | 3B |
| TX_D4 | J1.40 / J1.42 | R14_P / R14_N | B9 / B10 | GPIOR_P_14 / GPIOR_N_14 | 3A |
| TX_D5 | J1.9 / J1.11 | R03_P / R03_N | H6 / J6 | GPIOR_P_03_CDI26 / GPIOR_N_03_CDI27 | 3B |
Control and SPI
| AD9361 signal | Connector pin | Core board net | FPGA ball | FPGA pin name | Bank |
|---|---|---|---|---|---|
| ENABLE | J1.21 | R08_P | F7 | GPIOR_P_08_CLK11_P | 3B |
| EN_AGC | J1.23 | R08_N | E7 | GPIOR_N_08_CLK11_N | 3B |
| TXNRX | J1.28 | R06_P | F9 | GPIOR_P_06_CDI20 | 3B |
| RESETB | J1.30 | R06_N | F10 | GPIOR_N_06_CDI21 | 3B |
| SPI_ENB | J1.51 | R13_P | C8 | GPIOR_P_13 | 3A |
| SPI_CLK | J1.53 | R13_N | B8 | GPIOR_N_13 | 3A |
| SPI_DO | J1.55 | R10_P | D6 | GPIOR_P_10_CLK9_P | 3A |
| SPI_DI | J1.57 | R10_N | C7 | GPIOR_N_10_CLK9_N | 3A |
| RX_EXT_LO | J2.51 | L17_P | B4 | GPIOL_P_17_EXTFB | 1B |
| TX_EXT_LO | J2.53 | L17_N | C4 | GPIOL_N_17 | 1B |
- AD9361 SPI_DO is an FPGA input, and SPI_DI is an FPGA output.
- RX_EXT_LO / TX_EXT_LO are AD9361 external local oscillator inputs connected to FPGA L17. When using the internal local oscillator, do not drive these pins from the FPGA (leave unused or configure as inputs).
- RX_D2 uses the CBSEL0 / CBSEL1 multiplexed pins; use them as ordinary I/O after configuration.
- AD9361 CTRL_IN / CTRL_OUT, GPO, AUXADC / AUXDAC and CLK_OUT are not connected on the core board. SYNC_IN passes through J1.3 to J3.57 and can be supplied by the base board.
- Module USB-C connects to the core board MCU USB interface and also supplies 5V to the core board, so a single USB cable provides both power and programming.