This page covers creating a Tiny60-Core project in Efinix Efinity, configuring I/O and clocks, programming and troubleshooting. For pins and ball locations, see Pinout.

Project Settings

Item	Value
Device family	Titanium
Device	Ti60F100S3F2
Speed grade (Timing Model)	I3 (corresponding to part number Ti60F100S3F2I3)
Reference clock	X1 → GPIOR_P_00_PLLIN0 (ball J5)

Bank Voltages

In the Interface Designer I/O bank settings, enter the following voltages to match the actual board supplies:

Bank	Voltage	Notes
1A, 2A, 3B, BL	1.8 V	Fixed on the board
1B, 3A	Same as VCCIO1B / VCCIO3A supplied by the expansion module	For example, 1.8 V with RF-AD9361

I/O standard (single-ended / differential) and VCCIO combinations must meet the Efinix Titanium datasheet requirements. All I/O in a bank must use standards compatible with that bank's voltage.

Clocks

• X1 is AC-coupled through a 10 nF capacitor to GPIOR_P_00_PLLIN0. Set this pin as a PLL reference clock input in Interface Designer, and set the PLL reference frequency and timing constraints to the nominal X1 frequency.
• Assign source-synchronous clocks from the expansion module to global clock pins: CLK8 – CLK11 on J1, CLK2 / CLK3 on J2 and CLK0 / CLK1 on J3. J2.45 (L18_P) can serve as PLLIN0, and J2.51 (L17_P) as PLL external feedback EXTFB.

MCU Communication

In addition to JTAG, the CH32V305 and FPGA have the following user interfaces. They are ordinary GPIO on the FPGA side and 1.8 V on the MCU side:

Interface	FPGA pins (balls)	MCU pins
UART (UART7)	GPIOR_P_19_PLLIN0 (A9) ← MCU TX; GPIOR_N_19 (A10) → MCU RX	PC2 / PC3
UART (UART3) or I²C2	GPIOR_P_05_CDI30 (H9), GPIOR_N_05_CDI31 (H8)	PB10 / PB11
SPI1 (MCU is master)	NSS GPIOT_P_01 (A4), SCK GPIOR_N_00_CDI22 (H5), MISO GPIOR_P_01_EXTFB (K10), MOSI GPIOR_N_01_CDI23 (J10)	PA4 / PA5 / PA6 / PA7

UART7 uses Bank 3A, whose VCCIO3A comes from the expansion module: it is unusable while VCCIO3A is unpowered, and must not be used when VCCIO3A is not 1.8 V. MCU firmware determines the actual use of each interface.

SRAM Loading and Flash Programming

The FPGA is programmed through the onboard CH32V305 USB-JTAG interface:

1. Connect a USB cable to USB-C on the base board or expansion module (for example, RF-AD9361 J3). USB D± connects to MCU PB6 / PB7 on the core board.
2. Complete synthesis and place-and-route in Efinity, then generate the bitstream.
3. Use the Tiny60-Core programming tool to write SRAM (lost at power-off) or in-package Flash (loaded automatically at power-on).
4. When configuration is complete, CDONE goes high and the DONE LED lights.

MCU firmware can be updated through the bottom-layer SWDIO / SWCLK test points (PA13 / PA14) using an SWD debugger such as WCH-Link. Reset signal CH32_RST is routed to J3.51.

Programming and Runtime Troubleshooting

Symptom	Checks
Computer does not detect the USB device	Check that 5 V reaches the core board, USB connects to the USB-C routed to J1 / J3, and MCU firmware is programmed
JTAG scan does not find the FPGA	Check VDD_0V95 / VDD_1V8 and whether the base board or expansion module is holding CRESETN low
Programming completes but DONE stays off	Check that the bitstream targets Ti60F100S3F2 and that the expansion module supplies VCCIO1B (the TEST_N pull-up connects to VCCIO1B)
No output from Bank 1B / 3A I/O	Check that the expansion module supplies VCCIO at J2.39 – J2.42 and that Interface Designer bank voltages match the actual supplies
Incorrect reference clock in timing report	Check that the PLL reference frequency matches the nominal X1 frequency and that the reference input is GPIOR_P_00_PLLIN0