Tiny60-DL is a 50 mm × 36 mm development base board for the Tiny60-Core board. The core board mounts on base board J1, rotated 90°. A single USB-C cable connects both the core board FPGA programming MCU and the base board debug probe MCU through the onboard USB hub, and powers the entire assembly. The base board also provides a JTAG / UART debug header, camera FPC connector, FPGA clock interface and core board MCU SPI interface.

Tiny60-DL system block diagram: USB-C connects through CH334P to the base board debug probe (port 2) and core board MCU (port 3)

Key Specifications

Item	Specification
Compatible core board	Tiny60-Core (J1: Hirose DF40HC(3.0)-60DS-0.4V(51) receptacle, 3.0 mm board-to-board spacing)
USB	USB-C (J2, USB 2.0, sink), CH334P four-port hub: port 2 connects to the base board debug probe, port 3 to the core board MCU
Debug probe	WCH CH32V305GBU6 (U1): JTAG / SWD and UART3 routed to a 2 × 5 header, jumper-selectable 1.2 / 1.8 / 3.3 V I/O voltage
Core board MCU firmware update	Two pogo pin holes align with the core board SWCLK / SWDIO test points
Camera	21-pin FPC (HX FPC 0.3-21P), 8-bit DVP + I²C + UART + 5 V
FPGA interface	JST BM06B-SRSS 6-pin: two FPGA Bank 1A clock input pairs (CLK0, CLK1) + 5 V
MCU interface	JST BM06B-SRSS 6-pin: core board MCU SPI2 + FPGA CRESETN
Power	USB-C 5 V; 3.3 / 1.8 / 1.2 V supplied by the core board
Indicator	LED1: controlled by the debug probe MCU (PA8)
PCB	4-layer, 1.56 mm board thickness (JLC04161H-3313), 4 M3 plated mounting holes (connected to GND)
Dimensions	49.96 mm × 36.02 mm, R3.0 mm rounded corners

Development Resources

Document	Contents
Hardware Architecture	USB topology, debug probe connections, power, interface circuits and onboard components
Pinout	J1, JTAG and CH-VIO pin diagrams, FPC and two JST interface pin tables
Mechanical	Dimension drawings, core board mounting position, hole and connector coordinates, PCB stackup and impedance
Getting Started	Assembly, jumpers, power-on, FPGA programming and troubleshooting
Debug Interface	JTAG / SWD / UART header, debug voltage selection and core board MCU firmware update

Quick Start

1. Install the core board: Align Tiny60-Core J3 with base board J1 and press down as described in Getting Started. Fit 3.0 mm standoffs at the 4 Ø2.0 mm core board mounting holes (M2 screws have almost no clearance in Ø2.0 mm holes; M1.6 screws are recommended).
2. Set the CH-VIO jumper: Select 1.2 / 1.8 / 3.3 V to match the target I/O voltage. Select 1.8 V when debugging Tiny60-Core 1.8 V signals.
3. Connect USB: Connect USB-C to the computer. The hub connects the computer to both the core board programming MCU and the base board debug probe.
4. Provide VCCIO: Without an expansion module, core board Bank 1B / 3A have no I/O supply and TEST_N loses its pull-up. Install an expansion module such as RF-AD9361, or tie VCCIO1B / VCCIO3A to 1.8 V as described in Getting Started.
5. Program the FPGA: Generate a bitstream in Efinity and write it using the Tiny60-Core programming tool. The core board DONE LED lights when programming is complete.