The base board connects through J3 on the core board's bottom layer, supplies power and USB, and can receive DVP camera signals and two Bank 1A differential I/O pairs. For pins, see Pinout; for footprint coordinates, see Mechanical · Base Board Mounting Projection.

Ready-made base board

Tiny60-DL is the official development base for this core board: a USB hub, a debug-probe MCU, JTAG / UART headers, a camera FPC and an FPGA clock header. Use this page when designing your own base board.

Mating Connector

Item	Requirement
Core board side	J3: Hirose DF40C-60DP-0.4V(51) header, bottom layer, back to back with J2
Base board side	Hirose DF40 series 60DS-0.4V(51) receptacle; board-to-board spacing depends on the receptacle model
Position and pin 1	Place using the "J3 pin 1" coordinate in Base Board Mounting Projection
Mounting	4 Ø2.0 mm mounting holes (H1 – H4)
Clearance	FPGA, MCU, oscillators and J4 are on the bottom layer; allow height clearance for these components on the base board within the core board projection

Power Supply

Net	J3 pins	Direction	Requirement
5V	52 / 54 / 56 / 58 / 60	Input	Core board's only supply input (can also be supplied by the expansion module through J2)
VDD_3V3	46 / 48 / 50	Output	Core board TMI7003 CH2; available for low-current base board loads
VDD_1V8	40 / 42	Output	Core board TMI7003 CH1
VDD_1V2	34 / 36	Output	Core board TMI7003 CH3
GND	1 / 2 / 7 / 8 / 13 / 14 / 19 / 20 / 25 / 26 / 31 / 32 / 37 / 38 / 43 / 44 / 47 / 53 / 59	—	Connect all to ground

• 5V also connects to J2 on the core board. The base board and expansion module must not both supply 5V unless one side has an ideal diode or power-selection circuit.
• The core board TMI7003 supplies 3.3 V, 1.8 V and 1.2 V to the core board, expansion module and base board. Limit base board loading; generate supplies for high-current loads from 5V on the base board itself.

USB

J3.28 / J3.30 carry USB_P / USB_N, connected in parallel on the core board with the MCU (PB7 / PB6) and J1.4 / J1.6.

• For base board USB-C, route D± to J3.28 / J3.30 at 90 Ω differential impedance, connect VBUS to 5V, and provide separate 5.1 kΩ pull-downs on CC1 / CC2.
• Connect only one USB-C port at a time. If the expansion module (such as RF-AD9361) also has USB-C, both ports' D± and VBUS are connected in parallel.

Reset and Control

Signal	J3 pins	Notes
CRESETN	55	FPGA reset, active low; core board has a 10 kΩ pull-up to 1.8 V; pull low with an open-drain output or pushbutton on the base board
CH32_RST	51	MCU reset, active low; core board has a 10 kΩ pull-up to 1.8 V
SYNC_IN	57	Pass-through to J1.3; can supply a synchronization signal to an expansion module such as AD9361
CH32_PB12 – PB15	16 / 18 / 22 / 24	MCU SPI2 (NSS / SCK / MISO / MOSI), 1.8 V logic

FPGA I/O

Differential pair	J3 pins (P / N)	FPGA balls	Function
L07	4 / 6	F4 / F5	Bank 1A, CLK0
L08	10 / 12	E4 / E5	Bank 1A, CLK1

Bank 1A is fixed at 1.8 V. These two pairs can serve as base board clock inputs to the FPGA or ordinary I/O. Core board trace lengths are L07 9.99 / 10.13 mm and L08 9.30 / 9.71 mm.

DVP Camera Signals

The 8-bit DVP data, PIXCLK, VSYNC, HSYNC, I²C, UART and RSTn on J4 connect only to J3 on the core board, not to the FPGA or MCU. To use the camera, connect these signals to the target processor on the base board. The core board supplies camera power (3.3 V and TIR_5V0) at J4. For J4-to-J3 pin mapping, see Pinout · DVP Camera.