RF-AD9361 is a 2T2R software-defined radio module based on the ADI AD9361, measuring 25 mm × 34 mm. The module includes the RF front end, reference clock and 1.3 V supplies. Two Hirose DF40 60-pin board-to-board connectors carry the LVDS data interface, SPI, control signals and power to an FPGA carrier board. The carrier supplies 3.3 V and I/O power and implements the data interface logic.

RF-AD9361 system block diagram: 4 SMA RF ports on the left, FPGA carrier connection through J1 / J2 on the right

Key Specifications

Item	Specification
Transceiver	AD9361 (BGA144, 10 mm × 10 mm), 2 transmitters and 2 receivers
RF range	70 MHz – 6.0 GHz (IC); onboard TCM1-63AX+ baluns rated for 10 – 6000 MHz
Channel bandwidth	200 kHz – 56 MHz (IC)
RF interface	4 × SMA: TX1A, RX1A, RX2A, TX2A; 50 Ω single-ended, converted to differential through 1:1 baluns
Data interface	LVDS; RX / TX each use 6 data pairs + FRAME + clock; up to 61.44 MSPS per channel
Reference clock	Onboard 40 MHz passive crystal (X1), connected to XTALP / XTALN
Configuration interface	4-wire SPI (SPI_ENB / CLK / DI / DO)
Board-to-board connectors	J1, J2: DF40HC(3.0)-60DS-0.4V(51), 0.4 mm pitch, 3.0 mm stacking height
Supply inputs	VDD_3V3 (onboard 2 × ADP1755 → 1.3 V), VDD_GPO (AD9361 VDD_INTERFACE / VDD_GPO)
USB	Type-C (J3, bottom layer); VBUS and D± pass through the board-to-board connectors to the carrier
PCB	10-layer HDI, 1.532 mm board thickness, 4 Ø2.0 mm non-plated mounting holes
Dimensions	25.00 mm × 34.00 mm, R2.0 mm rounded corners

IC-level specifications are from the AD9361 datasheet. The usable frequency range and RF performance also depend on the onboard baluns and matching networks; see Hardware Architecture.

Development Resources

Document	Contents
Hardware Architecture	RF paths, clocks, power tree, grounding and onboard components
Pinout	All 120 J1 / J2 pins, signal directions, AD9361 ball locations and USB-C
Mechanical	Dimension drawings, mounting hole and connector coordinates, carrier mounting projection, PCB stackup and impedance
Carrier Board Design	Mating connectors, power requirements, LVDS routing, on-module trace lengths and FPGA bank voltages
Driver Configuration	ADI HDL interface, Linux device tree, no-OS initialization parameters and power-on checks

Quick Start

1. Prepare the carrier: Place two DF40C-60DP-0.4V(51) headers as described in Carrier Board Design, supply VDD_3V3 and VDD_GPO, and connect the LVDS signals to the same FPGA differential I/O bank.
2. Install the module: Face the connectors toward the carrier, align J1 / J2 and press down vertically. Secure the four Ø2.0 mm mounting holes with 3.0 mm standoffs (M2 screws have almost no clearance in Ø2.0 mm holes; M1.6 screws are recommended).
3. Connect antennas or cables: For conducted tests, connect TX ports to instruments through attenuators. Do not connect them directly to a spectrum analyzer or receiver input.
4. Load the FPGA design and driver: Use the ADI axi_ad9361 IP and configure LVDS mode and the 40 MHz reference clock as described in Driver Configuration. Read back the product ID over SPI before debugging the data link.

RF Port ESD

The SMA ports connect directly to the AD9361 RF pins through baluns and DC-blocking capacitors, without additional ESD protection. Discharge static electricity before connecting or disconnecting cables or antennas.