This page describes FPGA bank voltage assignments, clocks, configuration and JTAG, MCU connections and power design. For connector pins, see Pinout.

I/O Banks and Voltages

Bank	VCCIO source	Voltage	Connections
1A	VDD_1V8 (VCCIO1A_4B, G2)	1.8 V	J2: L05, L06; J3: L07, L08
1B	VCCIO1B (D3), supplied through J2.40 / J2.42	Set by expansion module	J2: L09 – L13, L17, L18
2A	VDD_1V8 (VCCIO2A_2B, A6)	1.8 V	MCU: T01_P
3A	VCCIO3A (C9), supplied through J2.39 / J2.41	Set by expansion module	J1: R10 – R14; MCU: R19
3B	VDD_1V8 (VCCIO3B_4A, G9)	1.8 V	J1: R02 – R04, R06 – R09; MCU: R00, R01, R05; X1: R00_P
BL	VDD_1V8 (VCCIO33_BL, J3)	1.8 V	JTAG, CRESET_N, CDONE

• VCCAUX (B6, G6) connects to VDD_1V8; VCC / VCCA (C6, D7, E6, F6, G5, H7, A2, A7, K7) connects to VDD_0V95.
• Bank 1B and 3A have only decoupling capacitors on the core board, with no supply connection. The expansion module must connect J2.39 – J2.42 to suitable voltages; see Expansion Modules · VCCIO.
• REF_RES_1A / 1B / 2A / 3A / 3B / 4A each connect to ground through 10 kΩ (R1 – R6). VQPS (A5) connects to ground.

Clocks

Clock	Connection	Notes
X1	OT201650MJBA4SL oscillator, powered by VDD_1V8, EN tied high	Output AC-coupled through C3 (10 nF) to GPIOR_P_00_PLLIN0 (J5, Bank 3B)
X2	CSACM8M00G530000R0, 8 MHz resonator, C5 / C6 22 pF	CH32V305 main clock
External clocks	J1: CLK8 – CLK11; J2: CLK2, CLK3, PLLIN0 (L18_P), EXTFB (L17_P); J3: CLK0, CLK1	Inputs from the expansion module or base board; see Pinout

Configuration and JTAG

Signal	FPGA ball	Onboard connection
TCK / TMS / TDI / TDO	K3 / K4 / K5 / J4	CH32V305 PC10 / PD2 / PC12 / PC11, each with a 10 kΩ pull-up to 1.8 V
CRESET_N	K1	10 kΩ pull-up to 1.8 V, 0.1 µF to ground; also routed to J2.24 and J3.55
CDONE	H3	10 kΩ pull-up to 1.8 V; drives the DONE LED through Q1
NSTATUS / TEST_N	C5 / D5	Each has a 10 kΩ pull-up to VCCIO1B
SSL_N / CCK / CDI0 / CDI1	J1 / J2 / H2 / H1	Not connected on the board

There is no external SPI Flash, and SSL_N / CCK / CDI0 / CDI1 have no external connections. Ti60F100S3F2 integrates configuration Flash in the package (see the Efinix Ti60 datasheet for capacity and programming methods) and loads from it at power-on. JTAG supports SRAM loading and Flash programming. The DONE LED lights when CDONE goes high (configuration complete).

TEST_N and VCCIO1B

The TEST_N pull-up connects to VCCIO1B. Without an expansion module supplying VCCIO1B, TEST_N has no pull-up, and the FPGA may fail to enter user mode.

MCU

CH32V305GBU6 VDD connects to 3.3 V and its I/O supply VIO to 1.8 V, so MCU I/O is 1.8 V. Pins connected to the FPGA have no level shifting, so the FPGA banks on those pins must also run at 1.8 V.

CH32V305 pin	Function	Connection
PB6 / PB7	USB D− / D+	J1.6 / J1.4 and J3.30 / J3.28 (all three connected in parallel)
PC10 / PD2 / PC12 / PC11	JTAG TCK / TMS / TDI / TDO	FPGA K3 / K4 / K5 / J4
PC2 / PC3	UART7 TX / RX	FPGA A9 (R19_P) / A10 (R19_N), Bank 3A
PB10 / PB11	UART3 TX / RX, or I²C2 SCL / SDA	FPGA H9 (R05_P) / H8 (R05_N), Bank 3B
PA4 / PA5 / PA6 / PA7	SPI1 NSS / SCK / MISO / MOSI	FPGA A4 (T01_P) / H5 (R00_N) / K10 (R01_P) / J10 (R01_N)
PB12 – PB15	SPI2 NSS / SCK / MISO / MOSI	J3.16 / J3.18 / J3.22 / J3.24
NRST	Reset	10 kΩ pull-up to 1.8 V, 0.1 µF to ground; routed to J3.51
PA13 / PA14	SWDIO / SWCLK	Bottom-layer SWDIO, SWCLK test points (MCU firmware programming)

UART7 connects through Bank 3A: it is usable only after VCCIO3A is powered, and VCCIO3A must be 1.8 V to match the MCU's 1.8 V I/O. UART3 and SPI1 use the fixed 1.8 V Bank 2A / 3B and are independent of the expansion module.

Power

Power tree: 5 V input; B1 first generates 0.95 V, then its PG enables the three U3 outputs

Rail	Source	Feedback resistors	Loads
VDD_0V95	B1 TPS62826A (3 A), L4 0.47 µH	R23 58.3 kΩ 0.1% / R25 100 kΩ 0.1%	FPGA VCC, VCCA
VDD_1V8	U3 TMI7003 CH1, L1 2.2 µH	R17 200 kΩ / R18 100 kΩ	FPGA VCCAUX and 1A / 2A / 3B / BL, X1, MCU VIO, J2.36 / 38, J3.40 / 42
VDD_3V3	U3 TMI7003 CH2, L2 2.2 µH	R19 453 kΩ / R20 100 kΩ	MCU VDD, DONE LED, J2.44 – 50, J3.46 – 50, J4
VDD_1V2	U3 TMI7003 CH3, L3 2.2 µH	R21 100 kΩ / R22 100 kΩ	Routed only to J2.28 / 30 and J3.34 / 36; unused on the board
TIR_5V0	U4 NCP163 (5.0 V, 250 mA low-noise LDO)	—	J4.39 / 40 camera module

Power-on sequence: B1 EN connects to 5 V, so 0.95 V starts as soon as 5 V is present. B1 PG (R24 100 kΩ pull-up) connects to U3 EN1 – EN3, enabling 1.8 V, 3.3 V and 1.2 V together after 0.95 V is established. U4 EN connects to 5 V and starts alongside 0.95 V.

Onboard Components

Reference	Component	Function
U1	Ti60F100S3F2I3	FPGA, bottom layer
U2	CH32V305GBU6 (QFN28 4 × 4 mm)	USB programming / communication MCU, bottom layer
U3	TMI7003 (QFN20 3 × 3 mm)	Triple buck converter, 1.8 / 3.3 / 1.2 V
B1	TPS62826ADMQR (1.5 × 1.5 mm)	0.95 V core supply
U4	NCP163AMX500TBG	Camera 5 V LDO
X1	OT201650MJBA4SL	FPGA reference clock, bottom layer
X2	CSACM8M00G530000R0	MCU 8 MHz clock, bottom layer
DONE, Q1	0603 LED, PBSS4612PA	Configuration complete indicator
J1, J2	DF40C-60DP-0.4V(51)	Expansion interfaces, top layer
J3	DF40C-60DP-0.4V(51)	Base board interface, bottom layer
J4	WP7B-P040VA1-R8000	DVP camera interface, bottom layer

The board has 91 components in total; unlisted parts are decoupling capacitors and pull-up / pull-down resistors.