Tiny60-Core is a compact FPGA core board based on the Efinix Titanium Ti60F100, measuring 22.95 mm × 17.85 mm. It includes all FPGA supplies, a reference clock and a CH32V305 USB programming / communication MCU. Two top-layer DF40 connectors (J1, J2) connect expansion modules such as the RF-AD9361 RF Module; bottom-layer J3 connects the base board, and J4 connects a DVP camera module.

Tiny60-Core system block diagram: top-layer J1 / J2 connect expansion modules; bottom-layer J3 connects the base board, and J4 connects the camera

Key Specifications

Item	Specification
FPGA	Efinix Ti60F100S3F2I3 (Titanium, FBGA100, 0.5 mm ball pitch), with in-package configuration Flash
User I/O	12 differential pairs on J1, 9 on J2 and 2 on J3 (all usable as single-ended I/O), across Bank 1A / 1B / 3A / 3B
Clocks	X1 oscillator (OT201650MJBA4SL, 1.8 V) connects to GPIOR_P_00_PLLIN0; connectors also provide 8 global clock input pairs (CLK0 – CLK3, CLK8 – CLK11) and 1 PLLIN0
MCU	WCH CH32V305GBU6 (RISC-V, 1.8 V I/O): USB, FPGA JTAG, 2 UARTs, SPI
Supply input	5 V (J3 or J2); onboard TPS62826A + TMI7003 generate 0.95 / 1.8 / 3.3 / 1.2 V, and NCP163 generates camera 5 V
Expansion interfaces	J1, J2: Hirose DF40C-60DP-0.4V(51) headers, top layer, 14.03 mm center spacing
Base board interface	J3: DF40C-60DP-0.4V(51) header, bottom layer, back to back with J2
Camera interface	J4: JAE WP7B-P040VA1-R8000, 40 pins, 8-bit DVP + I²C + UART + 3.3 V / 5 V
Indicator	DONE: lights when FPGA configuration is complete
PCB	10-layer HDI, 1.465 mm board thickness, 4 Ø2.0 mm plated mounting holes
Dimensions	22.95 mm × 17.85 mm, R1.91 mm rounded corners

Development Resources

Document	Contents
Hardware Architecture	Bank voltages, clocks, configuration and JTAG, MCU connections, power tree and power-on sequence, onboard components
Pinout	J1 – J4 pin diagrams, FPGA ball locations, banks and clock functions for each differential I/O pair
Mechanical	Dimension drawings, mounting hole and connector coordinates, base board mounting projection, PCB stackup and impedance
FPGA Development	Efinity project settings, bank voltages, clock constraints, programming and troubleshooting
Expansion Modules	Expansion module design rules, VCCIO connections, onboard trace lengths and RF-AD9361 pin mapping
Base Board Design	J3 mating connector, power, USB, DVP and reset signals

Quick Start

1. Connect VCCIO: The expansion module supplies VCCIO for Bank 1B / 3A through J2. Before using the core board alone, read Expansion Modules · VCCIO.
2. Apply power: Supply 5 V through base board connector J3 or an expansion module (such as the RF-AD9361 USB-C port).
3. Create a project: Select Ti60F100S3F2 and timing model I3 in Efinity, then configure bank voltages and pins as described in FPGA Development.
4. Program the FPGA: Connect to the onboard CH32V305 over USB and use the supplied programming tool to program the FPGA. The DONE LED lights when configuration is complete.