This page covers Tiny60-DL and Tiny60-Core assembly, power-on and FPGA programming. For FPGA project settings, see Tiny60-Core · FPGA Development.

Installing the Core Board

1. Face the core board bottom layer (FPGA side) down. Align core board J3 with base board J1, with their pin 1 positions matching. The core board is rotated 90° relative to the base board; see the dash-dot outline in Mechanical.
2. Press the DF40 connectors together vertically. Do not lever or insert them at an angle.
3. Fit 3.0 mm standoffs at S1 – S4 and secure the four core board corners with screws (M2 screws have almost no clearance in Ø2.0 mm holes; M1.6 screws are recommended).
4. If an expansion module such as RF-AD9361 is needed, install it on core board top-layer J1 / J2.

Jumpers and Interfaces

Item	Setting
CH-VIO	Select the debug probe I/O voltage with a jumper cap; see Pinout · CH-VIO Jumper
Camera	Connect to the base board FPC or core board J4; both expose the same signals
External clock	Use the FPGA 6-pin interface for CLK0 / CLK1 (1.8 V)

Power-On

1. Connect USB-C to a computer or 5 V USB power supply. 5 V reaches the core board through J1. The core board generates 0.95 / 1.8 / 3.3 / 1.2 V, returning 3.3 / 1.8 / 1.2 V to the base board.
2. The computer detects two devices through the CH334P hub: the core board MCU (FPGA programming) and the base board debug probe MCU. Device names depend on their firmware.
3. If the core board in-package Flash contains a configuration, the FPGA loads it automatically at power-on and the DONE LED lights.

Power Only Through the Base Board

5 V is directly connected between the base board, core board and expansion module. When using the base board, do not also supply power through the expansion module USB-C or other core board 5 V inputs.

FPGA Programming

1. In Efinity, select device Ti60F100S3F2 and speed grade I3 as described in Tiny60-Core · FPGA Development, then generate the bitstream.
2. Use the Tiny60-Core programming tool, select the USB device corresponding to the core board MCU, and write SRAM or in-package Flash.
3. The DONE LED lights when programming is complete. To reset the FPGA externally, pull CH32 interface pin 5 (CRESETN) low.

Using Only the Base Board and Core Board

The base board does not supply VCCIO for core board Bank 1B / 3A, nor does it connect to core board top-layer J1 / J2. Without an expansion module:

• Bank 1B and 3A have no I/O supply; their I/O and MCU UART7 cannot be used.
• The core board TEST_N pull-up also connects to VCCIO1B, so the FPGA may fail to enter user mode.

Connect VCCIO1B / VCCIO3A to 1.8 V on core board J2 before debugging, as described in Tiny60-Core · Expansion Modules.

Troubleshooting

Symptom	Checks
Computer does not detect any devices	Check that the USB cable supports data, base board USB-C is connected and CH334P has 5 V
Only one device is detected	Core board MCU missing: check that the core board is seated and its MCU firmware is programmed; debug probe missing: check that a jumper cap is installed on CH-VIO (the debug probe does not operate without I/O power)
DONE LED stays off	Check the bitstream device model, core board VCCIO1B supply and whether the CH32 interface is holding CRESETN low
No camera image	Camera signals do not pass through the FPGA or MCU; see Hardware Architecture · Other Interfaces