The base board CH32V305 (U1) connects to USB through CH334P port 2. Its hardware supports use as a JTAG / SWD debug probe and USB-to-UART bridge: signals are routed to the 2 × 5 JTAG header, and pogo pins connect to the core board MCU SWD interface. The debug protocol and host software depend on U1 firmware; this page covers hardware connections. For header pin assignments, see Pinout · JTAG Header.

Debug Voltage

The debug probe MCU I/O supply VIO is the voltage selected by the CH-VIO jumper. All JTAG header signals use this voltage as their high level, and pin 4 provides it to the target board as a reference.

1. Fit the CH-VIO jumper cap to match the target board I/O voltage (1.2 / 1.8 / 3.3 V).
2. Connect the target board and base board grounds (JTAG.10).
3. If the target board has its own power supply, do not connect JTAG.2 (5V).

Voltage Mismatch

The header signals have no level shifting. The voltage selected by CH-VIO must match the target board I/O voltage; otherwise, the target board or debug probe may be damaged.

JTAG / SWD Connections

Mode	Header pins used
JTAG	1 TCK, 5 TMS, 9 TDI, 3 TDO, 7 TRST (optional), 4 VIO, 10 GND
SWD	1 SWCLK, 5 SWDIO, 4 VIO, 10 GND
UART	6 TXD (debug probe transmit), 8 RXD (debug probe receive), 10 GND

• TCK, TMS, TDI and TDO each have a 100 Ω series resistor; UART signals each have 270 Ω series resistance, to limit current and reduce reflections.
• TRST (pin 7) also connects to core board MCU reset (J1.51). Driving TRST low resets the core board MCU.

Core Board MCU Firmware

The core board CH32V305 firmware handles FPGA programming. The base board provides two pogo pin holes directly below the core board SWCLK / SWDIO test points. Their nets are CH_TCK and CH_TMS, respectively, shared with JTAG header pins 1 and 5:

1. Check that pogo pins are installed in the base board SWCLK / SWDIO holes (solder them in if absent; see Mechanical for locations). The pogo pins contact the core board test points when the core board is installed.
2. Select 1.8 V on CH-VIO (the core board MCU uses 1.8 V I/O). Program the core board MCU firmware using the base board debug probe, or connect an SWD debug probe such as WCH-Link to JTAG header pins 1 / 5 / 4 / 10.
3. To reset the core board MCU, pull JTAG.7 (TRST) or core board J3.51 low.

Shared SWD Nets

JTAG header pins 1 / 5, base board U1 PA14 / PA13 and core board MCU SWD (with pogo pins installed) share the same nets. When an external debug probe accesses one MCU, the other MCU must not drive these two lines at the same time.

Base Board Debug Probe Firmware

U1 SWD (PA14 / PA13) is routed to JTAG header pins 1 / 5. An external SWD debug probe can program U1 firmware through the header. A CH-VIO jumper cap must be installed during programming (U1 I/O requires power). NRST has a 10 kΩ pull-up; U1 reset is not routed to the header.

Troubleshooting

Symptom	Checks
Target board does not respond	Check that CH-VIO matches the target voltage, grounds are connected and TCK / TMS are not contending with the core board MCU through the pogo pins
No UART data	Check that TXD / RXD are crossed (debug probe TXD to target RXD)
Core board MCU cannot be programmed	Check pogo pin contact with the test points, core board 3.3 V supply and whether another device is driving the SWD nets