This page lists connector, power, I/O level and routing requirements for an RF-AD9361 FPGA carrier board. See Pinout for pin definitions and Mechanical · Carrier Mounting Projection for footprint coordinates.

Ready-made carrier

Tiny60-Core mates directly with this module through its top-side J1 / J2 and supplies VDD_GPO = 1.8 V. See Tiny60-Core · RF-AD9361 Pin Mapping for the FPGA ball of every signal.

Mating Connectors

Item	Requirement
Module side	J1, J2: Hirose DF40HC(3.0)-60DS-0.4V(51), 60-pin receptacles
Carrier side	2 × Hirose DF40C-60DP-0.4V(51), 60-pin headers, 3.0 mm board-to-board spacing when mated
Placement	Use the coordinates in Carrier Mounting Projection; connector centers are 14.03 mm apart
Pin 1	Header pin 1 must coincide with the "pin 1" coordinates in the table (module top-layer coordinates require left-right mirroring)
Mounting	4 Ø2.0 mm mounting holes with 3.0 mm standoffs

Power Requirements

Supply	Voltage	Current	Description
VDD_3V3	3.3 V	Design for ≥ 2 A recommended	Two linear LDOs; input current is approximately the sum of the two 1.3 V loads; schematic budget is 800 mA per rail
VDD_GPO	1.8 V or 2.5 V	Tens of mA	Supplies both AD9361 VDD_INTERFACE and VDD_GPO; must match VCCO of the connected FPGA bank
5V	—	—	Connected directly to module USB-C VBUS; use on the carrier as needed

• Refer to the AD9361 datasheet for the allowed VDD_INTERFACE range in LVDS mode. Common combinations are LVDS_25 at 2.5 V for Xilinx 7-series HR banks and LVDS at 1.8 V for HP banks.
• The module LDOs start outputting immediately when VDD_3V3 powers up; PG is not exposed. The FPGA should hold RESETB low during power-up, then release reset and initialize the AD9361 after VDD_3V3 and VDD_GPO are stable.
• The LDO voltage drop is 2 V. At the schematic budget (2 × 800 mA), the two ADP1755 devices dissipate approximately 3.2 W in total; actual power depends on the transmit/receive configuration. Keep continuous ground copper beneath the module on the carrier and avoid placing heat-generating components within the module projection.

5V and USB-C Power

USB-C VBUS connects directly to the J2 5V pins on the module, without a switch or reverse-current blocking device. If the carrier has another 5 V supply, add an ideal diode or power-selection circuit on the carrier to prevent backfeeding the USB host. CC1 / CC2 have 5.1 kΩ pull-downs, allowing only default USB power; PD negotiation is not supported.

Default Control Signal Levels

RESETB, ENABLE, TXNRX, EN_AGC, SYNC_IN, SPI_ENB and CTRL_IN0–3 have no onboard pull-ups or pull-downs. These pins are high-impedance before FPGA configuration completes. Recommended carrier connections:

Signal	Carrier connection
RESETB	10 kΩ pull-down to keep the AD9361 in reset before FPGA configuration
SPI_ENB	10 kΩ pull-up to VDD_GPO to prevent unintended selection
ENABLE, TXNRX, EN_AGC, SYNC_IN, CTRL_IN0–3	10 kΩ pull-downs, or continuously driven by the FPGA
CTRL_OUT0–7, GPO_0–3	May be left unconnected when unused
AUXADC	Ground or leave unconnected when unused; see the AD9361 datasheet for the input range
RX_EXT_LO, TX_EXT_LO	Leave unconnected when using the internal LOs

LVDS Routing

1. Differential impedance: Route all LVDS pairs at 100 Ω differential over a continuous ground plane. Keep intra-pair length mismatch within 0.1 mm.
2. Same bank: Place all 16 differential pairs in the RX and TX groups in the same I/O bank (or adjacent banks within the same clock region). Bank VCCO must equal VDD_GPO.
3. Clock pins: Connect DATA_CLK to dedicated FPGA clock inputs (MRCC / SRCC on Xilinx devices) as the RX sampling clock.
4. Termination: Enable on-chip 100 Ω differential termination at the FPGA receiver (DATA_CLK, RX_FRAME, RX_D; Xilinx DIFF_TERM). Enable on-chip termination at the AD9361 receiver (FB_CLK, TX_FRAME, TX_D) in the driver.
5. Group length matching: Match lengths within the RX group (DATA_CLK, RX_FRAME, RX_D0–5) and within the TX group (FB_CLK, TX_FRAME, TX_D0–5) separately. Include the on-module trace lengths below. The two groups do not need to match each other; residual skew can be compensated by AD9361 data interface delay settings.

On-module trace lengths from AD9361 balls to connector pads (from the PCB, excluding vias):

Signal group	Differential pairs	On-module length
RX	DATA_CLK, RX_FRAME, RX_D0 – RX_D5	17.6 – 18.3 mm
TX	FB_CLK, TX_FRAME, TX_D0 – TX_D5	29.6 – 30.0 mm
USB	USB_P / USB_N (Type-C → J1)	46.4 – 46.8 mm

Other Interfaces

• USB: Route USB_P / USB_N at 90 Ω differential to a SoC USB PHY or USB bridge IC. Leave unconnected when unused.
• SPI: Keep SPI_CLK at or below the frequency configured in the driver (10 MHz in the ADI device tree example). Keep traces short and avoid long parallel runs alongside LVDS traces.
• GPO: AD9361 GPO drive capability is limited. Use buffers to drive external RF switches or power amplifiers.