The RF-AD9361 digital interface matches the ADI FMCOMMS2/3 evaluation boards in LVDS mode, so ADI HDL reference designs, the Linux IIO driver and the no-OS driver can be used directly. This page lists settings specific to the module hardware. See the ADI HDL, ADI Linux and no-OS repositories for obtaining and building the ADI projects.

Hardware-Specific Configuration

Setting	Value	Hardware basis
Data interface	LVDS	Only LVDS differential pairs are exposed
Reference clock	40 MHz, crystal mode	X1 connects to XTALP / XTALN
Channel mode	2T2R (1T1R is also configurable)	All 4 SMA ports are connected
RX port	Port A balanced input (RX1A, RX2A)	Ports B / C are grounded
TX port	Port A (TX1A, TX2A)	TXB is biased and not exposed
SPI	4-wire, CPHA = 1	SPI_DO is routed separately
Reset	RESETB active low, GPIO-controlled	J1.30

FPGA Interface

Use the ADI HDL axi_ad9361 IP in LVDS mode (CMOS_OR_LVDS_N = 0). The table maps module signals to the ADI reference design system_top ports:

Module signal	system_top port	Description
DATA_CLK_P / N	rx_clk_in_p / rx_clk_in_n	Dedicated clock input pins
RX_FRAME_P / N	rx_frame_in_p / rx_frame_in_n
RX_D[5:0]_P / N	rx_data_in_p[5:0] / rx_data_in_n[5:0]
FB_CLK_P / N	tx_clk_out_p / tx_clk_out_n
TX_FRAME_P / N	tx_frame_out_p / tx_frame_out_n
TX_D[5:0]_P / N	tx_data_out_p[5:0] / tx_data_out_n[5:0]
ENABLE / TXNRX	enable / txnrx	Driven by axi_ad9361
RESETB	gpio_resetb
SYNC_IN / EN_AGC	gpio_sync / gpio_en_agc
CTRL_IN0–3 / CTRL_OUT0–7	gpio_ctl[3:0] / gpio_status[7:0]
SPI_ENB / CLK / DI / DO	spi_csn / spi_clk / spi_mosi / spi_miso

Add PACKAGE_PIN assignments to the constraints file according to the carrier schematic. Example for a Xilinx 7-series HR bank with VDD_GPO = 2.5 V:

# RX: enable on-chip differential termination on the FPGA
set_property -dict {IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports {rx_clk_in_p rx_clk_in_n rx_frame_in_p rx_frame_in_n}]
set_property -dict {IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports {rx_data_in_p[*] rx_data_in_n[*]}]
# TX: termination is inside the AD9361
set_property IOSTANDARD LVDS_25 [get_ports {tx_clk_out_p tx_clk_out_n tx_frame_out_p tx_frame_out_n}]
set_property IOSTANDARD LVDS_25 [get_ports {tx_data_out_p[*] tx_data_out_n[*]}]
# Control and SPI use the same bank voltage
set_property IOSTANDARD LVCMOS25 [get_ports {enable txnrx gpio_resetb gpio_sync gpio_en_agc gpio_ctl[*] gpio_status[*]}]
set_property IOSTANDARD LVCMOS25 [get_ports {spi_csn spi_clk spi_mosi spi_miso}]

# DATA_CLK up to 245.76 MHz (2T2R, 61.44 MSPS)
create_clock -name rx_clk -period 4.0 [get_ports rx_clk_in_p]

For an HP bank, replace LVDS_25 / LVCMOS25 with LVDS / LVCMOS18 and set VDD_GPO to 1.8 V.

Linux Device Tree

Starting from ADI's adi-fmcomms2.dtsi, make sure the following properties match the module (adjust node names and the SPI bus for the platform):

ad9361_clkin: clock@0 {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	clock-frequency = <40000000>;        /* X1 40 MHz */
	clock-output-names = "ad9361_ext_refclk";
};

&spi0 {
	adc0_ad9361: ad9361-phy@0 {
		compatible = "adi,ad9361";
		reg = <0>;
		spi-cpha;
		spi-max-frequency = <10000000>;
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
		#clock-cells = <1>;

		adi,2rx-2tx-mode-enable;
		adi,frequency-division-duplex-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;  /* FB_CLK, TX_FRAME, TX_D termination */
		adi,rx-rf-port-input-select = <0>;      /* RX1A / RX2A, balanced input */
		adi,tx-rf-port-input-select = <0>;      /* TX1A / TX2A */
		/* Crystal mode: do not set adi,xo-disable-use-ext-refclk-enable */

		reset-gpios = <&gpio0 RESETB_GPIO GPIO_ACTIVE_LOW>;
	};
};

Replace RESETB_GPIO with the GPIO number connected to J1.30 on the carrier. To switch transmit/receive states through the ENABLE / TXNRX pins from FPGA logic, also add adi,ensm-enable-pin-pulse-mode-enable and adi,ensm-enable-txnrx-control-enable. By default, the state machine is controlled over SPI.

no-OS Initialization Parameters

When using no-OS, set the following in AD9361_InitParam:

.reference_clk_rate = 40000000UL,          /* X1 40 MHz */
.xo_disable_use_ext_refclk_enable = 0,     /* Crystal mode */
.two_rx_two_tx_mode_enable = 1,
.frequency_division_duplex_mode_enable = 1,
.lvds_mode_enable = 1,
.lvds_bias_mV = 150,
.lvds_rx_onchip_termination_enable = 1,
.rx_rf_port_input_select = 0,              /* RX1A / RX2A */
.tx_rf_port_input_select = 0,              /* TX1A / TX2A */

Fill in reset, SPI and GPIO descriptors according to the platform's no-OS project.

Power-On Checks

1. Power: Measure VCC1_1V3 and VCC2_1V3 at 1.3 V (across C2 / C5). VDD_GPO must match FPGA bank VCCO.
2. Read the ID over SPI: After releasing RESETB, read register 0x037. The value bitwise-ANDed with 0xF8 should be 0x08 (the low 3 bits are the silicon revision; a typical reading is 0x0A). On Linux:

   cd /sys/kernel/debug/iio/iio:device0      # Device corresponding to ad9361-phy
   echo 0x37 > direct_reg_access && cat direct_reg_access

3. Driver initialization: AD936x Rev <n> successfully initialized in dmesg indicates that the BBPLL has locked and data interface calibration has passed.
4. RF loopback: Connect TX1A to RX1A through an attenuator of at least 30 dB. Set the same LO frequency and confirm reception of the transmitted tone in IIO Oscilloscope or iio_readdev.

Initialization Failures

Symptom	Checks
ID reads 0x00 or 0xFF	RESETB released, SPI_ENB polarity, SPI mode (CPHA = 1), VDD_GPO powered
BBPLL does not lock	Reference clock configured for 40 MHz crystal mode (external reference not selected)
Data interface calibration fails (digital tune failed)	rx_clk_in connected to dedicated clock pins, FPGA-side DIFF_TERM, LVDS pair polarity and group length matching
No received signal	Port A selected, antenna or cable connected to the corresponding SMA