Digital IDE (DIDE) is a user-friendly and efficient self-developed development tool for digital engineers. DIDE can run on all common platforms (Windows, Linux, macOS). For engineers who frequently work via SSH to connect to internal network servers, DIDE also supports various functions for remote development.
We are dedicated to the development philosophy of file structure and project structure, and with the help of standardized, simplified, and visual project management systems, IP management systems, and a wealth of auxiliary components, we assist downstream developers in meeting the needs of agile development, verification, and team collaboration during the research and development process. For upstream users, DIDE helps FPGA manufacturers reduce the costs associated with expanding and maintaining the software development ecosystem.
Our github repo 👇
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email: sterben.nitcloud@gmail.com | zhelonghuang@mail.ustc.edu.cn
QQ group: 932987873
If you encounter any issues during use, feel free to contact the administrators in the QQ group. Responses will be provided as soon as possible.
One-Click Simulation: Select the module to be simulated and click the simulation button to directly invoke independent simulation tools (e.g., Icarus Verilog).
One-Click Synthesis: Select the module to be synthesized, click the synthesis button to generate a netlist, and render it in the netlist view.
Top-Level Module Definition: Right-click the module to be set as the top-level, and choose to set it as the design or simulation top-level.
Export Module Dependencies: Right-click the module to export, and choose to export it as a filelist.f file.
Improved Rendering Stability: Fixed known bugs and enhanced the structure tree rendering for backend debugging.
Support for Xilinx File Structures: Added functionality to convert standard Xilinx file structures into the plugin’s standard file structure.
User Library Path Issue Resolved: Fixed the issue preventing user library paths from being imported.
Enhanced Instance Generation: Added support for command-line selection and autocomplete.
Improved Fast Simulation: Fixed known bugs in the fast simulation feature.
File Deletion Features Removed: Eliminated all functionalities that might delete files.
Testbench Template Generation Removed: Removed the feature for generating testbench templates.
Support for Efinix FPGA Development Environment: Added compatibility for Efinix FPGA development tools.
Port Table Description Fix: Resolved the disordered description column issue (GitHub #78, #77).
Default Syntax Diagnostics Removed: Removed the local default syntax diagnostic feature.
ToolBar Support: Added toolbar features for search, zoom, positioning, and marking.
Simulation Waveform Rendering: Supports line and step waveform rendering.
Waveform Drag and Grouping: Added drag-and-drop functionality with grouping support.
Enhanced Data Format Display: Added support for binary, octal, decimal, hexadecimal, and standard floating-point formats.
Waveform Multi-Select Deletion: Enabled the deletion of multiple waveforms simultaneously.
Waveform Save Feature: Added functionality to save waveforms.
Relative Time Calculation: Added support for relative time calculations.
Zero-Second Lock Bug Fix: Fixed the bug preventing locking at 0s.
First of all, thank you for your use and feedback. Any better ideas about this plugin can be published under both Zhihu and github, if it is the use of the problem please move to github instead of Zhihu. Thank you for your cooperation.
In addition, when posting an issue, please provide a detailed description of the problem you are experiencing, focusing on the following sections
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Please paste the source code if it is a special case (to better reproduce the problem)
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Thank you for using and providing feedback! If you have suggestions for improvement, feel free to post them on Zhihu or GitHub. However, for issues encountered during use, please post them on Github instead of Zhihu. Your cooperation is appreciated.
When submitting an issue, please include the following details:
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Info
All features and designs of this plugin are independently developed, with a focus on establishing our own standards, definitions, and characteristics. As such, requests to replicate features from other similar plugins will not be supported.
